The use of PLLs in communications over the years has become an ever-growing trend. New applications with specific synchronization requirements demand complex and flexible PLLs. Economy and the desire for integration require that PLLs support multiple application scenarios, each requiring different synchronization clock criteria. User configurable flexibility has become an essential part of new PLLs.
In a hierarchical timing network, it is desirable to place inexpensive equipment on the line cards at the edge of the network. Wander and jitter filtering is then performed by fewer timing cards with higher quality oscillators further up the timing chain. This works well for a traditional system that derives timing information from physical pulses in the form of electrical signals on the network and is configured with PLLs arranged in a cascaded fashion, with the output of one PLL feeding the input of the next. However, in a Timing over Packet (ToP) switched network, wherein timing information is derived from a timing packets using a clock recovery algorithm, it is desirable to implement the clock recovery algorithm on the line cards and to use the output of a filter of the timing card to drive the PHYs (physical interfaces) on the line cards that time stamp incoming timing packets. This arrangement improves the quality of the clock recovered by the line card by removing the effects of the inexpensive local oscillator used on the line card. Additionally, it simplifies the timing card design because no ToP data needs to be transferred up the timing chain. The timing card can operate with only electrical clock signals as inputs and outputs. A side effect of this configuration however is that the timing card PLL is inside the feedback loop of the ToP clock recovery algorithm. This arrangement creates a multi loop PLL system. In the traditional (non-ToP) PLL system based on electrical signals the two PLLs will be cascaded as shown in FIG. 1, where PLL1 is in the line card and PLL2 is in the timing card. As long as the bandwidth of the line card PLL1 is much higher than that of the timing card PLL2, the overall system transfer function will be defined by the timing card PLL2 transfer function.
A block diagram of a ToP system with the timing card PLL2 inside the feedback loop of the line card PLL1 is shown in FIG. 2. Unlike the cascaded PLL system, the bandwidth of this multi-loop PLL is a function of bandwidth of the PLLs on both the timing card and the line card.
FIG. 3 shows a typical prior art ToP line card/timing card system in a first configuration. The clock recovery module implementing the clock recovery algorithm is located on the timing card. This arrangement requires a complex data interface between the two cards to transfer time stamps and other connection data.
An alternative solution not forming part of the prior art and disclosed in co-pending patent application Ser. No. 61/927,013 filed Jan. 14, 2014, is to place the clock recovery module on the line card as shown in FIG. 4. This second configuration greatly simplifies the interface between the timing card and the line card, and is closer to traditional PLL systems employing electrical signals where the timing card PLL is mainly used to clean up the output wander of the PLL on the line card.
Both the above configurations constitute multi-loop PLL systems where one PLL is inside the feedback loop of the other PLL. In the case of FIG. 3, the line card PLL1 is in the feedback loop of the clock recovery algorithm on the timing card while in the case of FIG. 4, the timing card PLL2 is in the feedback loop of the clock recovery algorithm. Although the system of FIG. 4 requires at least three PLLs, PLL3 is set to a much higher bandwidth than PLL2, so it does not affect the transfer function of the system as a whole. Its role is to perform frequency conversion between the timing card and the PHY.
Also, since the line card PLL1 in the configuration of FIG. 3 has much higher bandwidth than the clock recovery algorithm on the timing card, even though the line card PLL1 is in the feedback loop of the clock recovery algorithm, it does not affect its bandwidth. The clock recovery module residing on the timing card can take advantage of the high quality local oscillator that is typically used o the timing cards to generate less output phase wander originating from the local oscillator.
In the configuration of FIG. 4, where the ToP clock recovery is performed on the line card there are two challenges. Since the bandwidth of the timing card PLL2 can be comparable to that of the clock recovery algorithm, the overall transfer function will be affected by the timing card PLL2. In this case, the timing recovery algorithm needs to be designed in such a way as to compensate for the effect of the timing card PLL2. Also, since the clock recovery module resides on the line card it needs to handle the high amount of oscillator wander due to the uncompensated, low quality crystal oscillators typically used on the line cards.
Because there are more of them, the quality of local oscillator on line cards is typically much lower than on the timing cards because it would not be cost effective to use high quality oscillators. In the configuration of FIG. 3, with the clock recovery module on the timing card, this is not an issue since the line card PLL1 has much higher bandwidth than the timing recovery algorithm. As a result it can effectively filter out all the wander originating from the local oscillator on the line card as the line card PLL1 acts as a high pass filter. In configuration of FIG. 4 where the clock recovery module resides on the line card, the timing card PLL2 bandwidth has to be made narrower so as to filter the jitter originating from the clock recovery algorithm found on the line card. As a result, the timing card PLL2 bandwidth is not high enough to filter out the drift and wander due to the low quality local oscillator employed on the line card. A temperature compensated (TCXO) or oven-controlled (OCXO) crystal oscillator is required. These types of oscillators are more expensive and bulkier compared to uncompensated oscillators.